1. Field of the Invention
The invention relates generally to the fabrication of semiconductor integrated circuit structures, and more particularly to the formation of buried split word line structures in memory cells.
2. Description of the Related Art
Semiconductor memories store bits of information in arrays of memory cells. For example, a dynamic random access memory (DRAM) cell typically includes an access field effect transistor (FET) and a storage capacitor. Some types of memory cells have buried word and bit lines. Memory cell word and bit lines may be buried by forming trenches in a semiconductor substrate and filling the trench with metal. Storage capacitors can be formed on the substrate surface or in the metal layers disposed above the substrate. For example, some types of DRAM cells have buried split word lines formed above buried bit lines. The buried split word lines extend in trenches orthogonal to the buried bit lines.
In fabricating semiconductor devices such as DRAMs, buried split word line structure is used to provide the memory cells in the adjacent rows for separately gating the access FETs therein. FIGS. 1A-E describe various processing techniques of a method of fabricating a buried split word line structure according to prior art. Referring to FIG. 1A, a crystalline silicon substrate 102 is covered with a layer of pad nitride 104, such as silicon nitride (Si3N4). Here, the pad nitride 104 serves as a hard mask. A photoresist (not shown) is deposited over the hard mask. The photoresist is exposed, patterned and etched to remove exposed portions. Then, the semiconductor wafer 100 is exposed to an etch process to transfer the photoresist pattern to the hard mask. Portions of the wafer 100 not covered by the hard mask are etched to form word line trenches within the wafer 100 using the hard mask to pattern the word line trenches. The substrate 102 is etched off to a preset depth, which forms the word line trenches 120. The photoresist is then removed prior to any further processing steps.
Referring to FIG. 1B, gate oxide (silicon dioxide, SiO2) 106 is formed on the exposed sidewalls 122 and bottom portions 124 in respective trenches 120, such as by In-situ steam generation (ISSG) oxidation. A glue layer 108, such as TiN, is formed on gate oxide 106. A conductive layer 110 is then formed over the working surface of the wafer 100, including filling the word line trenches 120 by chemical vapor deposition (CVD) of a refractory metal, such as tungsten or polysilicon. The working surface is then planarized, such as by chemical mechanical polishing/planarization (CMP). The glue layer 108 and the conductive layer 110 are dry etched (RIE) to form recesses in the word line trenches 120.
Referring to FIG. 1C, an oxide layer 112 is then deposited to fill the trenches 120. Portions of the oxide layer 112 are removed, such as by isotropic etching, leaving oxide spacers 112a and 112b along sidewalls 122 of the trenches 120. Afterward, the trenches 120 are etched through the conductive layer 110 and the glue layer 108 and particularly into the substrate 102 to form recesses in the substrate 102. Thus, the conductive layer 110 is split into two halves 110a and 110b and the glue layer 108 is split into two halves 108a and 108b along sidewalls 122 of the trenches 120 as shown in FIG. 1D. In FIG. 1E, isolation material 114, such as oxide, is formed over the working surface of the wafer 100, filling the trenches 120. CMP or other suitable planarization process is used to remove portions of isolation material 114 above the nitride layer 104.
In general, the height y of the split word lines (110a and 110b) is related to the channel length of the access FET while the width x of the split word lines (110a and 110b) is related to the sheet resistance of the gate region as shown in FIG. 1E. The etched depth of the glue layer 108 and the conductive layer 110 determine the height y of the split word lines. Consistency of the etched depth of the glue layer 108 and the conductive layer 110 depends on the capability of manufacturing equipments. In other words, the height y may vary greatly from equipment to equipment. On the other hand, both the thickness of the oxide spacers 112a and 112b and the lateral etching rate during the above tungsten/silicon etching process determine the width x of the split word lines. However, it is difficult to precisely control the above factors during etching processes. Thus, there is a need in the art to provide a more stable and consistent dimension of the buried split word line structure.